The Stack Machine Computer Project

MTM Scientific, Inc

The Stack Machine Computer Project was started after reading a book by Per Brinch Hansen: "Programming a Personal Computer". I was also intriqued by writings of Nikolaus Wirth about the Pascal programming language. The unique properties and simplicity of stack machine computers started my search for a suitable hardware platform for experimentation. I found a good summary of the historical stack machine hardware in a book by Philip Koopman: "Stack Computers, The New Wave", however obtaining off-the-shelf stack machine hardware was found to be quite challenging.

Several historical papers on the architecture, operation and hardware design of simple computers encouraged my consideration of building a stack machine computer from discrete components. Notably a paper by Bradford Rodriquez: "A Minimal TTL Processor for Architecture Exploration", and a paper by Richard Eckert: "Micro-Programmed Versus Hardwared Control Units: How Computers Really Work". Of these two papers, I found the Eckert description of simple a computer architecture to be especially amenable to construction and modification for my purposes.

Common to both simple computer descriptions was the use of an off-the-shelf Arithmetic Logic Unit (ALU), the 74LS181. Although obsolete, this particular IC has the wonderful ability to perform useful mathematical and logical operations while being controlled using TTL logic. The 74LS181 ALU is easily sourced on the secondary markets, such as EBAY.

Eckert Computer Architecture
Figure 1. Eckert Computer Architecture

In Figure 1, The components shown are as follows: PC is the Program Counter, MAR is the Memory Address Register, RAM is Random Access Memory (which can be RAM and ROM), MDR is the Memory Data Register, ACC is the ALU Accumulator, ALU is the Arithmetic Logic Unit, B is the 2nd ALU Register, IR is the Instruction Register and CONTROL is the Hardware Control Matrix.

In the basic implementation of the computer architecture described by Eckert, there is a 12 bit bus consisting of 8 data bits and 4 opcode bits. The computer has 8 instructions and a cyclic ring counter to provide 6 sequential trigger pulses. There are a total of 16 controls signals for controlling the individual IC's.  I combined these functions with the CLK (Clock), RST (Reset), GND (Ground) and +5V lines to create a 50 channel breadboard bus. This arrangement provided 4 unassigned channels for future development purposes.

Eckert Computer PCB Backplane
Figure 2. Eckert Computer Backplane PCB

The breadboard backplane to implement the Eckert Computer is shown in Figure 2. The design stategy was to make a basic backplane into which individual breadboarding cards could be inserted, tested and modified during the development phase. Since this platform is intended for development, the backplane includes LED logic level indication of all 50 channels of the bus. Also included is a manual toggle switch for single-stepping the bus clock.

Individual functional components of the computer architecture reside on individual cards. A partially assembled computer is shown in Figure 3. A card was created especially for the purpose of doing prototype circuit development. Also shown in Figure 3 is a view of the Ring Counter card.

Backplane with cards inserted
Figure 3. Computer Backplane with Cards