The TTL-Retro Computer Project

MTM Scientific, Inc

Working setup for the TTL-Retro Computer

The TTL-Retro Computer Project was started after reading a book by Per  Brinch Hansen: "Programming a Personal Computer". I was also intrigued by writings of Nikolaus Wirth about the Pascal programming language. The unique properties and simplicity of stack machine computers started my search for a suitable hardware platform for experimentation. I found a good summary of historical stack machines in a book by Philip Koopman: "Stack Computers, The New Wave", however obtaining off-the-shelf stack machine hardware was found to be quite challenging.

Specifications for the TTL-Retro

Primary Logic Family

74LS (Low-Power Schottky)

Clock Speed

1 MHZ

Bus Architecture

50 pin (“TTL-50” Bus)

Data Width

12 bits

Memory (ROM & SRAM)

64K (256 x 256, Equally Divided)

Controller Instructions

16

Keyboard

Apple II (with Parallel Output)

Display

40x2 LCD Module (4002)

Hardware Stacks

3 (Keyboard, Data & Return)

Arithmetic Logic Unit

74F181 (4 Bit Slice ALU, 3X)

Assembler

Custom Excel Spreadsheet

Programming Language

Threaded Interpretive Language


Several historical papers on the architecture, operation and hardware design of simple computers encouraged my consideration of building a stack machine computer from discrete components. Notably a paper by Bradford Rodriquez: "A Minimal TTL Processor for Architecture Exploration", and a paper by Richard Eckert: "Micro-Programmed Versus Hardwared Control Units: How Computers Really Work". Of these two papers, I found the Eckert description of a simple computer architecture using a hardware controller to be especially amenable to construction (and modification for my purposes) to create a stack machine computer.

The 16 native instructions for the TTL-Retro:

Hex Code

Mnemonic

Description

0

DTA

Direct To A

1

RCL

Recall

2

STO

Store

3

ALU

Arithmetic Logic Unit

4

JLA

Jump Loading A

5

MAB

Move A to B

6

JUM

Jump

7

JWE

Jump When Equal

8

PCA

Program Counter to A

9

PSH

Push

A

POP

Pop

B

INA

In to A

C

OUT

Out

D

JWG

Jump When Greater

E

JWM

Jump When Minus

F

CTR

Counter



Common to both simple computer descriptions was the use of an off-the-shelf Arithmetic Logic Unit (ALU), the 74LS181. Although obsolete, this particular IC has the wonderful ability to perform useful mathematical and logical operations while being controlled using TTL logic. The 74LS181 ALU is easily sourced on the secondary IC markets, such as on EBAY.

Eckert Computer Architecture
Figure 1. Eckert Computer Architecture

In Figure 1, The components shown are as follows: PC is the Program Counter, MAR is the Memory Address Register, RAM is Random Access Memory (which can be RAM and ROM), MDR is the Memory Data Register, ACC is the ALU Accumulator, ALU is the Arithmetic Logic Unit, B is the 2nd ALU Register, IR is the Instruction Register and CONTROL is the Hardware Control Matrix. We have annotated the original diagram with additional information for clarity, as shown in Figure 2. We have added hardware stacks to this architecture, which will be described separately.

Annotated Eckert Computer Diagram
Figure 2. Annotated Eckert Computer Architecture

In the basic implementation of the computer architecture (as described by Eckert) there is a 12 bit bus consisting of 8 data bits and 4 opcode bits. The computer has 16 (using a 4 bit to 16 decode) instructions and a cyclic ring counter to provide 6 sequential trigger pulses. There are a total of ~16 controls signals for controlling the individual IC's.  I combined these functions with the CLK (Clock), RST (Reset), GND (Ground) and +5V lines to create a 50 channel breadboard bus. The bus channel assigments are shown in the table. We refer to this as the "TTL-50" bus.

Eckert Computer PCB Backplane
Figure 3. Eckert Computer Backplane PCB

The breadboard backplane to implement the Eckert Computer is shown in Figure 3. The design stategy was to make a basic backplane into which individual breadboarding cards could be inserted, tested and modified during the development phase. Since this platform is intended for development, the backplane includes LED logic level indication of all 50 channels of the bus. Also included is a manual toggle switch for single-stepping the bus clock.  This basic backplane has since been expanded to 9 slots. Additional slots can be added with a riser card.

Individual functional components of the computer architecture reside on individual cards. A partially assembled computer is shown in Figure 4. A card was created especially for the purpose of doing prototype circuit development. Also shown in Figure 3 is a view of an early Ring Counter card. Subsequent versions of the card add a 1 MHZ clock crystal. The timer card also has an adjustable 555 timer version of the clock. During development the clock speed ranged from a manually actuated toggle switch, to a 555 timer (1HZ - 3KHZ), to a 1 MHZ crystal.

Backplane with cards inserted
Figure 4. Computer Backplane with Cards

The ALU card is shown in Figure 5. We have annotated the functions of the individual ICs for clarity. The ALU chips are combinatorial logic... they are NOT clocked. Therefore, special care and thought are required for the A and B register timings. The 74181 ALU chips are available in 2 different package sizes, 0.300" and 0.600" width. Note that we have used the narrow packages to keep the PCB layout more compact. This card, along with most other cards, has evolved during the development phase. We also added LED indicators for the 4 least significant bits of the A register.

View of the ALU card
Figure 5. The ALU card


The memory card was especially challenging to design because the MDR (Memory Data Register) must transfer data in both directions. This function is available in the 74F543 Octal Registered Transceiver. We forgot to tie the unused address lines on the SRAM to a stable logic state, which is why the resistors are present in the photo of Figure 6. (This condition exhibits as intermittent faults and was very difficult to troubleshoot!) Because of possible race conditions between the registers and SRAM we used a TTL delay line for some of the enable signals. We call this delayed clock signal the quadrature clock. The LEDs were added as an easy-to-read visible indicator of bus conditions on the board.  We added some capacitance to the power supply line as a precaution, but during the early phases of development the clock speed was very slow... only a few hertz. Noise has not been an issue. Note that the Memory Card was designed to also accept ROM programmable memory in the wide DIP packages.

Memory Board
Figure 6. The Memory card

We found it was challenging to do the initial checkout of individual board functions because of the tendency of TTL inputs to drift up to a weak logic 'high' level. Therefore we initially created a special board for the bus which tiea all lines to a logic level 'low' using an array of resistors.  We found that generally a 1K resistor was sufficient to pull lines to Logic "0". We eventually placed the resistors for anchoring the 12 bit bus to logic low on the backplane board. This approach has worked very well, and it is convenient to have the 12 bit bus always default to logic low.

Bus Termination Board
Figure 7. Bus Termination Card

Complete Eckert Computer Prototype
Figure 8. Complete Prototype Eckert Computer (Early version)

The original paper by Eckert is quite specific about the sequence of digital signals sent to control various operations, such as enabling signals on the bus and loading signals from the bus. We found that enabling and loading signals to the bus at the same time created undesirable race conditions. To avoid race conditions we implemented a short 50 ns delay in the loading operations by using EP9206-50 delay ICs as a quadrature clock. We took this approach to preserve the original design as closely as possible.

The boards were designed using the free design software from Express PCB.  We have used this software for PCB design for about 15 years and have been very happy with it. There is also a companion program available for creating circuit schematics. Most of the IC components have been purchased on the secondary market, such as EBAY.

We found installing indicator LEDs for many of the digital signal lines was invaluable. We also made a habit of labeling vias with the name of the signal, which made for very convenient test points using a multimeter probe. Placing the separate computer functions on individual cards was especially helpful for testing. This approach also allows individual cards to be revised and improved without affecting the other cards.  We implemented 3 stacks (Keyboard, Data & Return) using the same approach.

Input/Output communication with the computer remains a work in development. An APPLE II keyboard is used to put ASCII characters on the bus. The computer polls the keyboard looking for a key press. The keyboard output provides 8 bits in parallel. (The top bit indicates if a key press is new.) The keyboard masters the bus and sends data when it receives the appropriate signal from the computer. The TTL-Retro has no interrupts.

It is also possible to communicate with the computer using a laptop computer running a serial communcation program. We have found the program "Termite" works well for this purpose. A special interface card was designed which uses a Picaxe-20X2 microcontroller. The microcontroller handles the logic of sending ASCII characters to-and-fro to a serial port on the laptop. Over time we have reduced the use of a laptop for communication, and instead use an LCD display module card for output. Here is a photo of the Picaxe interface card.

Serial Card for communication with the laptop

Figure 9. Card for Serial Communication to Laptop

Presently we are in the process of writing an assembler that is hosted on the TTL computer. This is the classical idea of bootstrapping the operating system.  The instruction list for the computer has undergone extensive revision during the development phase. The instruction list was recently expanded with the addition of true 4-16 decode on the controller. Here is a partial list of mnemonics and their explanation.  All mnemonics are 3 characters. Instructions operate primarily on A, sometimes on A and B, and occasionally only on B. There are multiple conditional jumps available: including equality, relational and sign. (Not shown) The conditonal jumps do not require a compare instruction to set flags. The flags are set in real time using combinatorial circuitry on the ALU. A complete explanation of the language will be provided when the assembler is finished, as it is a work in progress. All these instructions are primitives, and execute in a single instruction cycle. We chose these mnemonics in an effort to make the assembly language appear somewhat like a terse higher level language. Here is a partial list:


Mnemonic Description
LAZ Load A with Zero
INC Increment A
MAB Move A to B
ADD Add A and B
OUT OUT A to Bus
POP POP from Stack
PSH PUSH to Stack
ASL Arithmetic Shift Left
DEC Decrement A
JLA Jump Loading A
INA IN A from Bus
NOP No Operation
NAN NAND of A with B
XOR XOR of A with B
AND AND of A with B
ORR OR of A with B
MBB Move B back to A
NTA NOT A
NTB NOT B (Result to A)
SUB Subtraction A-B
SEG Segment Memory Jump
PCA Program Counter to A


The TTL computer design includes hardware stacks. We have designed the stack interface such that multiple stacks can be added to the bus. For example, by adding 3 stack cards the computer can have a Data Stack, Keyboard Stack and a Return Stack. We will be saying more about this in the future.

Here is a list of bus assignments for the TTL-50:

TTL-50 Bus Assigments for the TTL-Retro

1              Data 0 (LSB), Also latched and sent as Bus #13 for microcode control of hardware

2              Data 1, Also latched and sent on Bus as #14 for microcode control of hardware

3              Data 2, Also latched and sent on Bus as #15 for microcode control of hardware

4              Data 3, Also latched and sent on Bus as #16 for microcode control of hardware

5              Data 4, Also latched and sent on Bus as #17 for microcode control of hardware

6              Data 5, Also latched and sent on Bus as #18 for microcode control of hardware

7              Data 6, Also latched but not sent on Bus (No room on Bus)

8              Data 7, Also latched but not sent on Bus (No room on Bus)

9              OP1 (LSB) Instruction Bit, or Data 8

10           OP2 Instruction Bit, or Data 9

11           OP3 Instruction Bit, or Data 10

12           OP4 (MSB) Instruction Bit, or Data 11

13           Microcode: CN (ALU*), or Decrement Selected Stack, or I/O Device Selection (Latched Bus #1)

14           Microcode: M  (ALU), or Increment Selected Stack, or I/O Device Selection (Latched Bus #2)

15           Microcode: S0 (ALU), or DATA Stack Select or I/O Device Selection (Latched Bus #3)

16           Microcode: S1 (ALU), or RETURN Stack Select, or I/O Device Selection (Latched Bus #4)

17           Microcode: S2 (ALU), or KEYBOARD Stack Select, or I/O Device Selection (Latched Bus #5)

18           Microcode: S3 (ALU),  or I/O Device Selection (Latched Bus #6)

19           IS Increment Stack Counter (on T3 for Push), A hardware control signal

20           DS Decrement Stack Counter (on T4 for Pop), A hardware control signal

21           T0 Timing (Ring Counter)

22           T1 Timing (Ring Counter)

23           T2 Timing (Ring Counter), Used for  Increment Counter (IP) & Load Instruction (LI), Hardware Sig

24           T3 Timing (Ring Counter)

25           T4 Timing (Ring Counter)

26           T5 Timing (Ring Counter)

27           >F “Greater Than” Flag (Signal from dedicated magnitude comparator  for ACC and B)

28           EP Enable Counter, A Hardware Signal

29           LP Load Counter, A Hardware Signal

30           LM Load Memory Address Register, A Hardware Signal

31           SJ Segment Jump, This is LCA signal sent to Segmented Memory Latch (Future use)

32           NF “Negative” Flag (Bit 12 of ACC Register)

33           BS Bus Send @ Ring T3 (Tells hardware I/O Device to Receive), A Hardware Signal

34           A  ALU calculation, Op defined by microcode bits (Bus 13,14,15,16,17,18), Hardware Signal

35           R  Read SRAM, A Hardware Signal

36           LD Load Memory Data Register from SRAM, A Hardware Signal

37           ED Enable Memory Data Register on Bus, A Hardware Signal

38           LA Load A Register from Bus, A Hardware Signal

39           W  Write SRAM, A Hardware Signal

40           EA Enable A Register on Bus, A Hardware Signal

41           EU Enable ALU Output on Bus, A Hardware Signal

42           LB Load B Register from Bus, A Hardware Signal

43           CLK TTL System Clock (1 MHZ, or 555 Timer, or Manual, or External)

44           BR Bus Receive @ Ring T3 (Tells hardware I/O Device to Send), A Hardware Signal

45           EF (“Equal” Flag, From a Hardware Comparison of ACC & B on ALU)

46           LS Load Stack from Bus, A Hardware Signal

47           ES Enable Stack to Bus, A Hardware Signal

48           QUAD CLK (Quadrature Clock w 150ns delay with respect to System Clock)

49           Ground

50           +5V

 

*See 74F181 datasheet for definition of the ALU setup bits



The TTL-Retro Computer System consists of the following cards as of August, 2021:
1) Backplane, Motherboard Card, 9 Slots with LED indicators on 50 bus lines, Rev B
2) LCD Display Card, uses 1602A Display Module,  Rev B
3) Memory Carrier Card, 64K ROM and SRAM, 256 Segments of 256 Memory Locations each, Rev D
4) Controller Card, Decodes Instructions and Controls Hardware, "TTL hardwired CPU", Rev D Longer
5) ALU & Latches Card, Uses 3pcs 74F181 ALU, 12 bits, Rev. M
6) Ring Counter Card (Creates pulses T0,T1,T2,T3,T4 and T5), 555 Timer Bus Clock, Rev D
7) Program Counter Card, 8 bit output to bus, Rev C (Eventually hope to combine cards 6 & 7)
8) Hardware Data Stack Card, Rev. B
9) Hardware Return Stack Card, Rev. B
10) Hardware Keyboard Stack Card
11) Apple II Keyboard Adapter Card, Rev. A
12) Picaxe I/O Card, Uses a  PICAXE-20X2 for Bus Monitoring and Serial Port I/0, Rev B

Here is a link to a Zip file containing the PCB design files for all of the cards mentioned in the above list. These files were created using the ExpressPCB application, which is available for free download at the company website. TTL-Retro PCB Design Files

Here is a link to a Zip file containing the PCB design files for the cards in Gerber format, which is useful for ordering. TTL-Retro PCB Gerber Files

(Please write to me by email if you are considering building this project, as I can provide updated design files. MTM 12/1/2021 )

TTL-Retro Memory Segment Organization for 1 Segment

 

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

1

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

2

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

3

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

4

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

5

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

6

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

7

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

8

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

ROM

9

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

10

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

11

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

12

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

13

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

14

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

15

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

16

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SEG



The memory organization of the TTL-Retro is unique. There are 256 memory segment of 256 Tribbles each. ( A Tribble is 12 bits.) Each memory segment is divided into 128 Tribbles of ROM (lower 0-127) and 128 Tribbles of SRAM (upper 128-255). The segment 0 is the home segment. Information sharing between segments is accomplished by using the triple stacks.  The ROM memory locations are programmed with code. The code is generated using a hex file editor and a Excel-based assembler running a simple substitution formula. The formula converts the 3 letter instruction mnemonics into equivalent Hex code. Because ROM and SRAM memory is not widely available for holding 12 bit wide data, we use dual chips capable of holding 16 bits. (The upper 4 bits are not used in ROM B.)  The code placed in ROM can be considered to be a combination of BIOS, Operating System, Assembler, Debugger and Interpreter.

We have written a Threaded Interpretive Language for the TTL-Retro. A well known example of a Threaded Interpretive Language is FORTH. We will be saying more about the language in future updates. Essentially the language provides the ability to code a complete language enviroment based on the user's requirements and preferred ASCII symbols. The language has extensibility. The language is stack-based. Here is a simple example of using the TTL-Retro language:

Line 1: > H2 H2 + .  (RET)
Line 2: 004  <

Here is the meaning of the symbols for the above:
">" is the user input prompt
"H2" Pushes a hexadecimal 2 to the Data Stack
"H2" Pushes another hexadecimal 2 to the Data Stack
"+" Add together the 1st and 2nd numbers on the Data Stack and put the result back on the Data Stack
"."  Pop the Data Stack and print the number on the LCD Display in hexadecimal format
"(RET)" Hit the Return Key to execute the line of code
"004" is the result of the addition, after the Return Key was hit
"<" is a user prompt to hit any key to continue
.  

Excel Assembler for TTL-Retro

Here is a photo of the cards comprising the computer as of September, 2020.

Computer Cards as of September, 2020

Resource List:

The paper by Eckert which forms the basis for this project. I am using the hardwired version of the controller. (There is no CPU.)

http://www.cs.binghamton.edu/~reckert/hardwire3new.html

The paper by Rodriguez that describes using the 74181 ALU in a homebrew 'PISC' computer.

https://bradrodriguez.com/papers/piscedu2.htm

The book by Koopman about Stack Computers, available online.

http://users.ece.cmu.edu/~koopman/stack_computers/index.html

A webpage by Sukuba with an excellent description of a 4-bit homebrew CPU.

http://jaromir.xf.cz/fourbit/fourbit.html

A book by Joseph D. Greenfield which describes construction and operation of a small computer very similar to the design discussed here: "Practical Digital Design Using ICs", 2nd edition, 1983. See especially Chapter 16. This is a great book!

Questions or Comments: Please email us at mtm@mtmscientific.com